Recently, a demand for flat-panel display apparatuses for use in large-screen display TV sets as well as portable telephones (such as mobile phones or cellular phones), notebook PCs, and monitors has expanded. For these display apparatuses, a liquid crystal or an organic EL is employed as a display device. An active matrix driving scheme is mainly adopted as a driving scheme of these display apparatuses. FIG. 17 schematically shows a typical configuration of a main portion connected to a pixel in a display unit of the display apparatus of the active matrix driving scheme. Referring to FIG. 17, the display apparatus of the active matrix driving scheme will be outlined.
Generally, a display unit 960 of the display apparatus of the active matrix driving scheme includes a semiconductor substrate on which pixel units 964 and thin-film transistors (TFTs) 963 are arranged in a matrix form (of 1280×RGB pixel columns×1024 pixel rows in the case of a color SXGA (Super Extended Graphics Array) panel, for example). In the case of a liquid crystal display apparatus, each pixel unit 964 includes a transparent electrode provided for each pixel unit and a liquid crystal sealed in between the semiconductor substrate and an opposing substrate provided facing the semiconductor substrate. One transparent electrode is formed on an entire surface of the opposing substrate. In the case of an organic EL display apparatus, the pixel unit 964 further includes a thin-film transistor that controls an organic EL element and current that flows through the organic EL element.
Turning on and off of a TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale voltage signal corresponding to a video data signal is supplied to the pixel unit 964. The gray scale voltage signal acts on the display device of each pixel unit, and brightness of each pixel unit is controlled. Display is thereby performed. In the case of the liquid crystal display apparatus, transmittance of the liquid crystal is changed by a potential difference between the gray scale voltage signal supplied to the pixel unit 964 and an opposing substrate voltage with respect to a back light inside the display apparatus. Display is thereby performed. On the other hand, in the case of the organic EL display apparatus, the thin-film transistor that controls the current according to the gray scale voltage signal supplied to the pixel unit 964 controls the current that flows through the organic EL element. Light-emitting brightness of the organic EL element is changed according to the current. Display is thereby performed. There are some organic EL display apparatuses where a current signal is directly supplied to the pixel unit from a driver. This specification handles the display apparatus where the gray scale voltage signal is supplied from the driver and the gray scale voltage signal is converted to the current signal at the pixel unit.
The scan signal is supplied to a scan line 961 from a gate driver 970, and a grayscale signal voltage is supplied to each pixel unit 964 from a data driver 980 through a data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, and a control signal that are necessary are supplied from the display controller 950 to each of the gate driver 970 and the data driver 980, and video data is supplied to the data driver 980. A supply voltage is given to each of the data driver 980 and the gate driver 970 from a power supply circuit 940. It is assumed that the video data that will be supplied to the data driver 980 is digital data.
Rewriting of data of one screen is performed in one frame period (of approximately 0.017 seconds, when driving at 60 Hz is performed). Data is successively selected every pixel row (every line) by each scan line, and the gray scale voltage signal is supplied to the pixel unit 964 from each data line within a selection period. There are also a configuration in which a plurality of pixel rows are simultaneously selected by a plurality of scan lines and a configuration in which driving is performed at a frame frequency of 60 Hz or more.
While the gate driver 970 needs to supply the scan signal of a binary value, the data driver 980 needs to drive the data line by the gray scale voltage signal of multi-valued levels in accordance with the number of gray scales. The data driver 980 includes, for each data line, a decoder that converts the video data to an analog voltage and an amplifier circuit that amplifies the analog voltage to output the so amplified analog voltage to the data line 962.
FIG. 18 is a block diagram showing a main portion of the data driver 980 in FIG. 17. The configuration of the data driver will now be described with reference to FIG. 18.
As shown in FIG. 18, the data driver 980 includes a shift register unit 16, a data register & latch unit 15, a level shifter group 14, a decoder group 10, a reference voltage generation circuit 11, an amplifier circuit group 12, a bias circuit 13, and output terminals S1 to Sq connected to a plurality of data lines (indicated by reference numeral 962 in FIG. 17), respectively.
The shift register unit 16 determines a data latch timing corresponding to an output, based on the clock signal CLK and a start signal. The data register & latch unit 15 receives video digital data, latches the digital data based on the timing determined by the shift register unit 16, and outputs the latched digital data to the level shifter group 14, responsive to a timing of an STB (strobe) signal. The level shifter group 14 converts low voltage signals received as bit data for respective outputs to high voltage signals and outputs the high voltage signals to the decoder group 10. Each of the shift register unit 16 and the data register & latch unit 15 includes a logic circuit, and is generally driven by a low voltage (0 to 3.3 V).
The reference voltage generation circuit 11 generates a plurality of reference voltage signals having mutually different levels determined according to the number of gray scales, and supplies the reference voltage signals to the decoder group 10. The decoder group 10 includes a plurality of decoder circuits corresponding to the number of the outputs. Each decoder selects the reference voltage signal corresponding to bit data output from the level shifter 14 and supplies the selected reference voltage signal to a corresponding amplifier circuit of the amplifier circuit group 12. Each amplifier circuit of the amplifier circuit group 12 receives a bias signal from the bias circuit 13, and amplifies and outputs a gray scale voltage signal to a corresponding output terminal of the output terminal group S1 to Sq, based on the reference voltage signal selected by each decoder of the decoder group 10. The number of gray scales is generally set to a power of two. The exponent of the power corresponds to the number of bits of data. When the number of bits is eight, the number of gray scales becomes 256, which is the eighth power of two.
Each decoder of the decoder group 10 includes a plurality of reference voltage lines of multi-valued (m-ary) levels corresponding to the number of gray scales and a plurality of switch transistors. The switch transistors controlled to be turned on and off according to data (binary data) of a predetermined number of bits, and the reference voltage signal corresponding to the data is selected from among reference voltage lines 70 of the multi-valued levels.
In recent years, the number of display colors has increased due to enhanced quality of a display apparatus. The number of display colors depends on the number of bits of video digital data and the number of voltage levels (number of gray scales) of gray scale voltage signals output from output amplifiers. In recent years, not only the number of display apparatuses for 6-bit data (64 gray scales), but also the number of display apparatuses for 8-bit data (256 gray scales) has increased. Further, display apparatuses for 10-bit data (1024 gray scales) have also been developed.
When the number of bits of data increases by two, the number of gray scales is quadrupled. The number of reference voltage lines and the number of switch transistors also increase according to the increase in the number of gray scales. Accordingly, the area of a decoder significantly increases, which significantly influences an increase in the chip cost of a data driver.
It is also demanded that the number of outputs per chip be increased and the number of driver LSIs mounted on the display apparatus be thereby reduced so as to reduce the cost of the driver mounted on the display apparatus.
With the increase in the number of outputs per chip, the necessity for narrowing pitches of each circuit corresponding to the number of outputs increases. In order to cope with these demands, there is an urgent need to reduce the area of the decoder group 10.
Patent Document 1 discloses a configuration of a decoder (ROM decoder) in which enhancement-type transistors and depletion-type transistors are arranged as a matrix and are divided into two decoders, in order to reduce the short-length direction size and area of a chip and to achieve reduction of the production cost reduction and reduction of the frame size of a liquid crystal display module. Patent Document 2 discloses a configuration of a digital-to-analog conversion circuit in which an amplifier that interpolates two reference voltages and amplifies and outputs a resulting voltage is employed in an amplifier circuit to reduce the number of reference voltages selected by a decoder and the area of the decoder.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2000-163018A (FIG. 3)    [Patent Document 2] JP Patent Kokai Publication No. JP-P2006-174180A (FIG. 7)